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technical data 1 november 2013, rev. 0 9 led display driver ic g eneral d escription the ik210 2 is a common cathode type led panel display driver with output size - 4 digits x1 3 segments or 7 digits x 10 segments and addition key scan function. serial interface provide connection with microprocessor. features IK2102DW sop - 28 ik2102tsd tssop - 28 ? wide operation voltage: 3.0v to 5.5v ? serial interface ? 8 - step dimming circuitry ? b uilt in osc generator (with external resistor regulation ) ? pulse segment current: 10 ma type (8 ma to 12 ma) @ v dd = 3.3v to 5.5v ? pulse segment current: 15 ma type (1 2 ma to 18 ma) @ v dd = 5.0v ? key scanning: 10 2 matrix ? operation temperature: - 40 to 85 c ? pkg option applications ? micro - computer peripheral device ? vcr set ? dvd combo set ? dmb player ta = - 40 to 85c f or all package ik2102 ordering information device package packing IK2102DW sop 28 tube IK2102DW t sop 28 t ape & reel ik2102tsd tssop 28 tube ik2102tsd t tssop 28 t ape & reel
ik2102 2 november 2013, rev. 0 9 pin assignment pin list and descriptions pin name i/o description pin rcur i a resistor is connected to this pin to determine the sg1 - sg13 output current and internal oscillation frequency. 1 di/o i/o data input - output pin this pin inputs serial data at the ris ing edge of the clock (starting from the bit). data output pin - n - channel, open - drain this pin outputs serial d ata at the falling edge of the clock. 2 clk i clock input pin this pin reads serial data at the rising edge and output data at the falling edge. 3 stb i serial interface strobe pin the data input after the stb has fallen is processed . when this pin is high, clk is ignored. 4 k1, k2 i key data input pins the data sent to these pins are latched at the end of the display cycle. (internal pull - low resistor). 5, 6 vdd - power supply 7, 21 sg1/ks1 to sg10/ks10 o segment output pins (p - channel, open drain) also acts as the key source. 8 - 17 sg11/gr7 to sg13/gr5 o segment / grid output pins 18 - 20 gnd - ground pins 22, 25, 28 gr4 to gr1 o grid output pins 23, 24, 26, 27
ik2102 3 november 2013, rev. 0 9 fig ure . block diagram the schematic diagrams of the input and output circuits are shown below. input pins: clk, stb & din (di/o)
ik2102 4 november 2013, rev. 0 9 input pins: k1, k2 input pins: rcur, sg1 to sg10 output pins: dout (di/o) , gr1 to gr4 output pins: sg1 1 / gr7, sg1 2 / gr6 & sg1 3 / gr5
ik2102 5 november 2013, rev. 0 9 functional description commands a command is the first byte (b0 to b7) inputted to ik2102 via di/o pin after stb p in has changed f rom high to low state. if for some reason the stb pin is set high while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. command 1 : display mode setting commands ik2102 provides 4 display modes setting as shown in the diagram below: as stated earlier a command is the first one byte (b0 to b7) transmitted to ik2102 via the din, di/o pin when stb is low. however, for these commands, bit 3 & bit 8 (b2 to b7) are given a value of 0. the display mode setting commands determine the number of segments and grids be used ( 4 grids to 13 segments , 7 grids to 10 segments ). a display command on must be executed in order to resume display. if the same mode setting is selected, no command execution is take place, therefore, nothing happens. when power is turned on, the mode 11 is selected. display mode settings: 00: 4 grids, (13 segments) 01: 5 grids, (12 segments) 10: 6 grids, (11 segments) 11: 7 grids, (10 segments) command 2: data setting commands the data setting commands executes the data write mode for ik2102. the data setting command, the bits5 and 6 (b4, b5) are given the value of 0. , bit7 (b6) is given the value of 1 while bit8 (b7) is given the value of 0. please refer to the diagram below. when power is turned on, bit 4 to bit 1 (b3 to b0) are given the value of 0.
ik2102 6 november 2013, rev. 0 9 command 3: address setting commands address setting commands are used to set the address of the display memory. the address is considered valid if it has a value of 00h to 0dh. if the address is set to 0eh or higher, the data is ignored until a valid address is set. when power is turned on, the address is set at 00h. please refer to the diagram below.
ik2102 7 november 2013, rev. 0 9 display mode and ram address data transmitted from an external device to ik2102 via the serial interface are stored in the display ram and are assigned addresses. the ram addresses of ik2102 are given below in 8 bit unit. command 4: display control commands the display control commands are used to turn on or off a display. it also used to set the pulse width. please refer to the diagram below. when the power is turned on, a 1/16 pulse width is selected and the displayed is turned of f. sg1 sg4 sg5 sg8 sg9 dig1 dig2 dig3 dig4 dig5 dig6 dig7 xxhl xxhu b0 b3 b4 b7 0dhu 0dhl 0chu 0chl 0bhu 0bhl 0ahu 0ahl 09hu 09hl 07hu 08hl 07hu 07hl 06hu 06hl 05hu 05hl 04hu 04hl 03hu 03hl 02hu 02hl 01hu 01hl 00hu 00hl sg12 sg13 lower 4 bits higher 4 bits
ik2102 8 november 2013, rev. 0 9 key matrix & key input data storege ram key matrix consists of 10 x 2 arrays as shown below: each data entered by each key (or any combination of keys) is stored as follows and read by a read command, starting from the last significant bit. when the most significant bit of the data (b0) has been read, the least significant bit of the next data (b7) is read. note: b2, b5, b6 and b7 do not care.
ik2102 9 november 2013, rev. 0 9 scanning and display timing 1 frame = tdisplay x (n+1) serial commumication format the following diagram shows the serial communication format. reception (data/command write)
ik2102 10 november 2013, rev. 0 9 transmission (data read) switching characteristic waveform switching characteristics waveform is given below. pw stb (strobe pulse width) 1s t clk - stb (clock - strobe time) 1s pw clk (clock pulse width) 400ns t setup (data setup time) 100ns t hold (data hold time) 100ns t pzl t plz
ik2102 11 november 2013, rev. 0 9 t tzl < 1s t tl z < 10s t tzh (rise time) 1s t thz (fall time) 10s aplications display memory is updated by incrementing addresses. please refer to the following diagram. where: command 1: display mode setting command 2: data setting command command 3: address setting command data 1 to data n: transfer display data ( 14 bytes max) command 4: display control command
ik2102 12 november 2013, rev. 0 9 the following diagram shows the waveforms when updating specific addresses. where: command 2 -- data setting command command 3 -- address setting command data -- display data
ik2102 13 november 2013, rev. 0 9 recommended software programming flowchart note s : 1. command 1: display mode setting 2. command 2: data setting commands 3. command 3: address setting commands 4. command 4: display control commands 5. when ic power is applied for the first time, the contents of the display ram are not defined: thus, it is strongly suggested that the contents of the display ram must be cleared during the initial setting.
ik2102 14 november 2013, rev. 0 9 power dissipation curve absolute maximum ratings * (unless otherwise stated, ta=25c, gnd=0v) parameter symbol rating units supply voltage vcc - 0.5 to + 6.0 v logic input voltage v i - 0.5 to v dd +0.5 v driver output current/pin i olgr 250 ma i ohsg - 18 ma maximum driver output current/total i total 25 0 ma operation temperature topr - 40 to +85 c storage temperature tstg - 65 to + 150 c * stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ik2102 15 november 2013, rev. 0 9 recommend ed operation range (unless otherwise stated, ta= - 40 to +85c, gnd=0v) parameter symbol min typ max unit logic supply voltage v dd 3.0 3.3 5.5 v dynamic current (see note) i dddyn . . 1 ma high - level input voltage v ih 0.7v dd . v dd v low - level input voltage v il 0 . 0.3v dd v note: test condition: set display control commands = 80h (display turn off state) electrical c haracteristics (unless otherwise stated, v dd = 3.3 to 5.5v , gnd = 0v, ta = - 40 to 85c) parameter symbol test condition min typ max unit high - level output current i ohsg1 v dd = 3.3 to 5 .5 v , v led =2.3v r = 12.1kohm sg1 to sg10 sg11/gr7 to sg13 /gr5 8 10 12 ma i ohsg2 v dd = 5v , v led =2.3v r = 8.07 kohm sg1 to sg10 sg11/gr7 to sg13 /gr5 12 15 18 ma digital input current i dg - - 0.2 - +0.2 ua low - level digital output current i oldg v o = 0.4v 4 - - ma segment high - level output current tolerance i tolsg v o = v dd =2.3v r = 12.1kohm sg1 to sg10 sg11/gr7 to sg13/gr5 - - 5 % high - level input voltage v ih - 0.7v dd - 0.3v dd v low - level input voltage v il - - - 0.3v dd v oscillation frequency f osc 1 v dd = 3.3 to 5 .5 v r = 12.1 k ohm 400 500 600 khz f osc 2 v dd = 5v , r = 8.07 kohm 500 750 900 k1, k2 pull down resistor r pd v dd =5.0v 40 - 100 k?
ik2102 16 november 2013, rev. 0 9 high - level output current oscillation frequency remark: graphs are only v dd = 5v
ik2102 17 november 2013, rev. 0 9 application circuit note: 1. circuit is for v dd =5v when v dd =3.3v, recommend r1 = 12.1kohm . 2 . the capacitor s (0.1uf) connected between the gnd and v dd pins must be located as near as possible to the ik2102 chip. 3 . ik2102 power supply is separate from the application system power supply. 4. for increase stability o f ic and reduce noise, c1 & c2 should be placed closer to 7 pin and c3 should be placed closer to 21pin. 5. ground of r1 should be routed directly to pin (28), not though common gnd. recommend value c1&c3 0.1u f - ceramics c2 47 0u f ~ 1000uf
ik2102 18 november 2013, rev. 0 9 application circuit (ik2102, key scan with diodes) note: 1. circuit is for v dd =5v when v dd =3.3v, recommend r1 = 12.1kohm 2 . the capacitor s (0.1uf) connected between the gnd and v dd pins must be located as near as possible to the ik2102 chip. 3 . ik2102 power supply is separate from the application system power supply 4. for increase stability o f ic and reduce noise, c1 & c2 shou ld be placed closer to 7 pin and c3 should be placed closer to 21pin. 5. ground of r1 should be routed directly to pin (28), not though common gnd. recommend value c1&c3 0.1u f - ceramics c2 47 0u f ~ 1000uf
ik2102 19 november 2013, rev. 0 9 application circuit (ik2102 without key scan) note: 1. circuit is for v dd =5v when v dd =3.3v, recommend r1 = 12.1kohm 2 . the capacitor s (0.1uf) connected between the gnd and v dd pins must be located as near as possible to the ik2102 chip. 3 . ik2102 power supply is separate from the application system power supply 4. for increase stability o f ic and reduce noise, c1 & c2 should be placed closer to 7 pin and c3 should be placed closer to 21pin. 5. ground of r1 should be routed directly to pin (28), not though common gnd. recommend val ue c1&c3 0.1u f - ceramics c2 47 0u f ~ 1000uf
ik2102 20 november 2013, rev. 0 9 recommended layout for gnd and vcc b u ses common cathode type led panel
ik2102 21 november 2013, rev. 0 9 package dimensions 28sop
ik2102 22 november 2013, rev. 0 9 symbol min max notes a 2.35 2.65 - a1 0.10 0.30 - b 0.33 0.51 9 c 0.23 0.32 - d 17.70 18.10 3 e 7.40 7.60 4 e 1.27 bsc - h 10.00 10.65 - h 0.25 0.75 5 l 0.40 1.27 6 n 28 7 0 o 8 o - notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact.
ik2102 23 november 2013, rev. 0 9 28 lead thin shrink small outline package ( tssop ) notes: dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 per side. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 per side. dimensions are measured at datum plane h. 4 dimensioning and tolerancing per asme y14.5m - 1994. dimensio n does not include dambar protrusion. allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. minimum space between protrusion and adjacent lead is 0.07mm. 6 dimension in ( ) are for reference only. 7 conforms to je dec mo - 153.

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